Data processing method for improving access performance of memory device and data storage device utilizing the same
US11614885B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Apr 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a predetermined memory block as an active memory block to receive data from a host device and accordingly record a plurality of logical addresses in a first mapping table. In response to a determination of recommending for activating one or more sub-regions of the memory device or delivering one or more Host Performance Booster (HPB) entries is required, the memory controller is further configured to update a second mapping table based on the first mapping table before delivering the HPB entries to the host device. The memory controller is further configured to generate the HPB entries according to the second mapping table after the second mapping table has been updated based on the first mapping table and deliver a packet comprising the HPB entries to the host device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.