Apparatus and method of a scalable and reconfigurable fast fourier transform
US11614945B2 · kind B2 · utility
0Cited by
0References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2019 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Oct 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel design for conflict free address generation mechanism is provided for reading data from Block RAM (BRAM) into a Fast Fourier Transform (FFT) module and writing back the processed data back to the BRAM. Also, a novel way of reducing a memory footprint by reducing a twiddle factor table size by taking an advantage of the symmetry property of twiddle factors is presented. Further, additional architecture-specific optimizations are provided, which involve a design of deeply pipelined butterfly modules and the BRAM accesses, parallel butterfly modules for a single FFT block and parallel FFT lane implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.