Processing computational models in parallel
US11615287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2020 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Feb 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an artificial intelligence chip for processing computations for machine learning models that provides a compute node and a method of processing a computational model using a plurality of compute nodes in parallel. In some embodiments, the compute node, comprises: a communication interface configured to communicate with one or more other compute nodes; a memory configured to store shared data that is shared with the one or more other compute nodes; and a processor configured to: determine an expected computational load for processing a computational model for input data; obtain a contributable computational load of the compute node and the one or more other compute nodes; and select a master node to distribute the determined expected computational load based on the obtained contributable computational load. Consequently, learning and inference can be performed efficiently on-device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.