Compiler for implementing memory shutdown for neural network implementation configuration
US11615322B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2019 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Oct 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the graph includes nodes representing options for implementing each layer of the machine-trained network and edges between nodes for different layers representing different implementations that are compatible. The compiler of some embodiments is also responsible for generating instructions relating to shutting down (and waking up) memory units of cores. In some embodiments, the memory units to shutdown are determined by the compiler based on the data that is stored or will be stored in the particular memory units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.