Methods and apparatus for scalable primitive rate architecture for geometry processing
US11615504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Apr 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.