Hardware accelerator with analog-content addressable memory (a-CAM) for decision tree computation
US11615827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2020 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Oct 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples described herein relate to a decision tree computation system in which a hardware accelerator for a decision tree is implemented in the form of an analog Content Addressable Memory (a-CAM) array. The hardware accelerator accesses a decision tree. The decision tree comprises of multiple paths and each path of the multiple paths includes a set of nodes. Each node of the decision tree is associated with a feature variable of multiple feature variables of the decision tree. The hardware accelerator combines multiple nodes among the set of nodes with a same feature variable into a combined single node. Wildcard values are replaced for feature variables not being evaluated in each path. Each combined single node associated with each feature variable is mapped to a corresponding column in the a-CAM array and the multiple paths of the decision tree to rows of the a-CAM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.