Semiconductor memory devices and methods of operating semiconductor memory devices
US11615861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Oct 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.