Electronic package structure and fabrication method thereof
US11615997B2 · kind B2 · utility
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13Claims
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Assignee
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Key dates
| Filing date | Mar 11, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Mar 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package structure includes: a substrate having an upper surface; a solder mask layer disposed on the upper surface of the substrate, at least one outer side of the solder mask layer being aligned with at least one outer side of the substrate; an electronic component with a first surface provided on the upper surface of the substrate; and a cavity located between the electronic component and the solder mask layer. A first surface of the cavity is formed by the first surface of the electronic component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.