Integrated circuit packages to minimize stress on a semiconductor die
US11616027B2 · kind B2 · utility
1Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2020 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Apr 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/163
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.