Delamination sensor
US11616029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Aug 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.