Semiconductor device and method of manufacturing the same
US11616036B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2022 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Mar 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/80986
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.