Amplifier gain-tuning circuits and methods
US11616475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Jan 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7239
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.