Phase interpolator and clock signal selector thereof
US11616502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Nov 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase interpolator capable of preventing a glitch from being generated during a clock signal switching operation and a clock signal selector thereof are provided. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. When the selector switches from selecting a first clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.