Hierarchical cyclic redundancy check techniques
US11616597B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2022 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Jan 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1867
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for wireless communications are described. In some wireless communications system, a wireless device may append, during a first encoding stage, a first set of cyclic redundancy check bits having a first size to each code block of a plurality of code blocks and may concatenate two or more code blocks from the plurality of code blocks into a first set of code blocks, each code block of the two or more code blocks including the appended first set of cyclic redundancy check bits. The wireless device may further append, during a second encoding stage, a second set of cyclic redundancy check bits having a second size to the first set of code blocks, and may transmit a message comprising the plurality of code blocks including the appended first set of cyclic redundancy check bits and the appended second set of cyclic redundancy check bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.