Digital signal routing circuit
US11617034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Mar 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R2420/01
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for digital signal routing. Signal routing is achieved with a multiply-accumulate block, which takes data from one or more data sources and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.