Arrayed time to digital converter
US11619914B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2022 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Jun 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S7/4865
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.