Lateral persistence directory states
US11620231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Aug 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.