Memory with symmetric read current profile
US11621037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Jul 14, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.