Positioning read thresholds in a nonvolatile memory based on successful decoding
US11621048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Jul 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/612
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.