Electronic chip memory
US11621051B2 · kind B2 · utility
1Cited by
10References
20Claims
0Family size
Assignees
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Key dates
| Filing date | Jan 12, 2022 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Jan 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.