Nano-wall integrated circuit structure with high integrated density

US11621349B2 · kind B2 · utility

Assignee

• University of Electronic Science and Technology of China · CN

Inventors

• Ping Li · Fujian, CN
• Yongbo Liao · Chengdu, CN
• Xianghe Zeng · Chengdu, CN
• Yaosen Li · Chengdu, CN
• Ke Feng · Lilburn, US
• Chenxi Peng · Chengdu, CN
• Zhaoxi Hu · Chengdu, CN
• Fan-Cheng Lin · Chengdu, CN
• Xuanlin Xiong · Chengdu, CN
• Tao He · Wilmington, US

Key dates

• Filing date: Jul 5, 2021
• Grant date: Apr 4, 2023
• Expiry date: Jul 5, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/117

Abstract

A nano-wall integrated circuit structure with high integration density is disclosed, which relates to the fields of microelectronic technology and integrated circuits (IC). Based on the different device physical principles with MOSFETs in traditional ICs, the nano-wall integrated circuit unit structure (Nano-Wall FET, referred to as NWaFET) with high integration density can improve the integration of the IC, significantly shorten the channel length, improve the flexibility of the device channel width-to-length ratio adjustment, and save chip area.