Enhancement mode startup circuit with JFET emulation
US11621708B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | May 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/33523
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A startup circuit adapted to be coupled to an input voltage supply and operable to supply an output voltage at an output terminal, the startup circuit including: a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal adapted to be coupled to the input voltage supply and the second current terminal coupled to the output terminal; a precharge circuit having a first terminal, a second terminal and a third terminal, the second terminal adapted to be coupled to the input voltage supply and the third terminal coupled to the first control terminal; a current limiter coupled to the precharge circuit, the first control terminal and the second current terminal; a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to the precharge circuit and the second control terminal adapted to be coupled to a control signal; and a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the first control terminal and the third control terminal is adapt…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.