Receiver performing background training, memory device including the same and method of receiving data using the same
US11621871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver included in a memory device includes a flag generator circuit, an equalizer circuit and an equalization controller circuit. The flag generator circuit is configured to, during a normal operation mode, generates a flag signal without an external command. The equalizer circuit is configured to, during the normal operation mode, receive an input data signal through a channel, generate an equalized signal by equalizing the input data signal based on an equalization coefficient, and generate a data sample signal including a plurality of data bits based on the equalized signal. The equalization controller circuit is configured to, during the normal operation mode, determine an amount of change in the equalization coefficient based on the flag signal, the equalized signal and the data sample signal, and perform a training operation in which the equalization coefficient is updated in real time based on the amount of change in the equalization coefficient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.