Queueing system with head-of-line block avoidance
US11621923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2020 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Feb 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.