High-side gate over-voltage stress testing
US11624769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2022 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | May 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2623
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.