Systems and methods for intelligent graph-based buffer sizing for a mixed-signal integrated circuit
US11625519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2022 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Apr 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for minimizing a total physical size of data buffers for executing an artificial neural network (ANN) on an integrated circuit includes implementing a buffer-sizing simulation based on sourcing a task graph of the ANN, wherein: (i) the task graph includes a plurality of distinct data buffers, wherein each of the plurality of distinct data buffers is assigned to at least one write operation and at least one read operation; (ii) the buffer-sizing simulation, when executed, computes an estimated physical size for each of a plurality of distinct data buffers for implementing the artificial neural network on a mixed-signal integrated circuit; and (iii) configuring the buffer-sizing simulation includes setting simulation parameters that include buffer-size minimization parameters and buffer data throughput optimization parameters; and generating an estimate of a physical size for each of the plurality of distinct data buffers based on the implementation of the buffer-sizing simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.