Integrated circuit and method of designing a layout thereof
US11625524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2019 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Dec 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first region corresponding to a first circuit and including a first dummy pattern and a first signal pattern which are spaced apart from each other by a width of a spacer in a conductive layer to extend in parallel in a first horizontal direction and a second region corresponding to a second circuit which is the same as the first circuit and including a second dummy pattern and a second signal pattern which are spaced apart from each other by the width of the spacer in the conductive layer to extend in parallel in the first horizontal direction. The first signal pattern and the second signal pattern are configured so that a first signal and a second signal corresponding to each other in the first circuit and the second circuit are respectively applied to the first signal pattern and the second signal pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.