Compiler for optimizing filter sparsity for neural network implementation configuration
US11625585B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2019 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Nov 7, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). In some embodiments, the compiler determines whether sparsity requirements of channels implemented on individual cores are met on each core. If the sparsity requirement is not met, the compiler, in some embodiments, determines whether the channels of the filter can be rearranged to meet the sparsity requirements on each core and, based on the determination, either rearranges the filter channels or implements a solution to non-sparsity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.