Three-dimensional semiconductor memory devices and methods of fabricating the same
US11626414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2020 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Jan 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.