Low-leakage regrown GaN p-n junctions for GaN power devices
US11626483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2020 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | May 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.