Hard mask and preparation method thereof, preparation method of Josephson junction, and superconducting circuit
US11626556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hard mask includes a silicon oxide layer provided on a bare silicon wafer; and a silicon nitride layer provided on the silicon oxide layer, wherein the silicon nitride is provided with a first pattern, the silicon oxide layer is provided with a second pattern corresponding to the first pattern, the first pattern and the second pattern have different shapes, and the first pattern and the second pattern are configured to assist in forming a Josephson junction on the bare silicon wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.