Patent · US Active

Control circuit and corresponding method

US11626880B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

STMicroelectronics SA

Inventors

Liliana Arcidiacono · Mascalucia, IT
Alessandro Nicolosi · Dresano, IT
Valeria Bottarel · Novara, IT

Key dates

Filing date	Oct 13, 2021
Grant date	Apr 11, 2023
Priority date	—
Expiry date	Oct 22, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17744
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.