Memory and apparatus for performing access control with aid of multi-phase memory-mapped queue
US11630601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2021 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Dec 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.