Reducing a number of commands transmitted to a co-processor by merging register-setting commands having address continuity
US11630672B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2020 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Nov 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic apparatus and a method for reducing the number of commands are provided. The electronic apparatus includes a central processor and a co-processor. The central processor generates a plurality of original register setting commands to set at least one bit of at least one register of the co-processor. The original register setting commands include a plurality of first original register setting commands, and a plurality of setting targets of the first original register setting commands have address continuity. The central processor merges the first original register setting commands to generate at least one merged register setting command. The central processor transmits the at least one merged register setting command to the co-processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.