Memory system architecture for multi-threaded processors

US11630691B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Robert Pawlowski · Beaverton, US
• Ankit More · San Mateo, US
• Jason Howard · Portland, US
• Joshua B. Fryman · Corvallis, US
• Tina C. Zhong · Gilbert, US
• Shaden Smith · Bellevue, US
• Sowmya Pitchaimoorthy · Hillsboro, US
• Samkit Jain · Hillsboro, US
• Vincent Cave · Hillsboro, US
• Sriram Aananthakrishnan · Portland, US
• Bharadwaj Krishnamurthy · Hillsboro, US

Key dates

• Filing date: Aug 24, 2021
• Grant date: Apr 18, 2023
• Expiry date: Aug 24, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1016
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.