Memory system and operating method thereof
US11630766B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2021 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Jan 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a plurality of memory chips, including a first memory chip and a second memory chip, and a controller. The controller includes a first central processing unit (CPU) to process a request received from a host, and a plurality of second CPUs to respectively control operations of the plurality of memory chips through a plurality of channels. An importance table is stored in the controller and includes information about a data programming method for data stored in the memory system, the information about the data programming method corresponding to importance information of the data. The second CPUs are configured to program at least some of the data in both the first memory chip and the second memory chip, based on the importance table, so that at least some of the data is stored in both the first memory chip and the second memory chip as same data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.