Semiconductor memory device using different crystallinities in storage node contact and a method of manufacturing the same
US11631677B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Jun 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.