Semiconductor device and method of manufacturing thereof
US11631768B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 1, 2019 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Mar 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.