Push-push frequency doubling scheme and circuit based on complementary transistors
US11632090B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2022 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Aug 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/541
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A push-push frequency doubler based on complementary transistors is provided. The first differential amplifier circuit receives a differential input signal having an initial frequency, and amplifies the amplitude of the second harmonic of the differential input signal to obtain a first signal. The second differential amplifier circuit receives the differential input signal with the initial frequency and amplifies the amplitude of the second harmonic of the differential input signal to obtain the second signal. Where, the first signal and the second signal are a set of differential signals with the same amplitude and a phase difference of 180°. The output load circuit extracts the second harmonic signal in the first and second signal respectively to obtain and output a pair of differential output signal with first output frequency whose value is twice of the initial frequency. As a result, the frequency doubler with differential output signal is realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.