Patent · US Active

Programmable fractional ripple divider

US11632119B1 · kind B1 · utility

1Cited by

3References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Sudipta Sarkar · Austin, US
Dimitrios Loizos · Sunnyvale, US
Mehran Mohammadi Izad · San Diego, US
Paul Lee · Sunnyvale, US
Steven E. Mikes · Apex, US
Manohar Nagaraju · Norristown, US

Key dates

Filing date	Apr 25, 2022
Grant date	Apr 18, 2023
Priority date	—
Expiry date	Apr 25, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH03K23/66
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.