Low power digital-to-time converter (DTC) linearization
US11632230B2 · kind B2 · utility
3Cited by
15References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2021 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Jul 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.