Data processing method for improving access performance of memory device and data storage device utilizing the same
US11636030B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2021 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Jun 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a memory device including multiple memory blocks corresponding to multiple sub-regions and a memory controller. The memory controller updates content of a read count table in response to a read command with a transfer length greater than 1 for designating more than one logical address to be read. The read count table includes multiple fields recording a read count associated with one sub-region and content of the read count table is updated by increasing the read count(s) associated with the sub-region(s) that logical addresses designated in the read command belong to. The memory controller selects at least one sub-region according to the content of the read count table and performs a data rearrangement procedure to move data of the logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.