Data processing method for improving access performance of memory device and data storage device utilizing the same
US11636042B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2021 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Jun 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a predetermined memory block as an active memory block to receive data from a host device and update content of a sub-region bit table in response to a write operation of the active memory block. The sub-region bit table includes one or more bits, each bit is associated with one or more sub-regions and a value of each bit is initially set to a default value. When data of a first logical address received from the host device is written in the active memory block, the memory controller is configured to determine which sub-region the first logical address belongs to and set the value of the bit associated with the sub-region that the first logical address belongs to to a predetermined value different from the default value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.