Fully integrated parity-time symmetric electronics
US11637355B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2021 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Dec 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01P1/36
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is disclosed. The integrated circuit includes a first resonator, a second resonator, and a coupling element. The first resonator has a first terminal and a second terminal, where the first resonator comprises a gain resistor, a gain capacitor, and a gain inductor in parallel and electrically coupling the first terminal with the second terminal. The second resonator has a third terminal and a fourth terminal, where the second resonator includes a loss resistor, a loss capacitor, and a loss inductor in parallel and electrically coupling the third terminal with the fourth terminal. The coupling element selectively couples the first terminal of the first resonator with the third terminal of the second resonator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.