Phased array with low-latency control interface
US11637371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2021 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Oct 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B7/086
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially—sequentially with regard to other beam-forming integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.