Synthesized clock synchronization between network devices
US11637557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2022 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Feb 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.