Segmented digital-to-analog converter with subtractive dither
US11637560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2021 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Nov 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/0678
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.