Clock recovery method, corresponding circuit and system
US11637683B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2021 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Jun 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/048
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.