Coding schemes for communicating multiple logic states through a digital isolator
US11637724B2 · kind B2 · utility
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16References
20Claims
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Key dates
| Filing date | May 28, 2021 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | May 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0266
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.