Image sensor including DRAM capacitor and operating method thereof
US11637980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2022 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Jan 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor includes a pixel array having a plurality of pixels; a row driver providing the pixel array with a boosting signal; and a read-out circuit configured to read out pixel signals output from pixels of a row line selected by the row driver. Each of the plurality of pixels includes: a first photodiode; a transmission transistor connected to the first photodiode; a first floating diffusion node, a second floating diffusion node, and a third floating diffusion node, which are connected to the transmission transistor to accumulate charges generated by the first photodiode; an LCG capacitor connected to the third floating diffusion node to accumulate the charges generated by the first photodiode; an MCG transistor connected between the first floating diffusion node and the second floating diffusion node; and an LCG transistor connected to the third floating diffusion node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.